IBIS Model File: virtex2.ibs
Version: 3.1
Release Date: 6/8/04
----------------------------

This file contains IBIS models for all Virtex-II I/O standards.  For more information about Virtex-II I/Os, please refer to Data Sheets and User Guides, available on the web:

http://support.xilinx.com/literature/index.htm


*** Notes

1. LVDS and LVPECL drivers require the use of external termination resistors to provide the correct voltage levels.  Please see the Virtex-II User Guide for more information.

2. To accurately model package parasitics, please include in your simulation a 65 ohm transmission line with 10-200ps of delay for flip-chip packages (FG*, FF*), and 10-100ps delay for wire-bond packages (BG*, CS*).  For more information, please see this Answer Record: http://support.xilinx.com/techdocs/11754.htm

3. The [Pin] and [Diff Pin] sections are provided to serve as examples only.  The models have been assigned arbitrary pin numbers that do not correspond to the package pinouts.  The IBISWriter program, part of Xilinx implementation software, can take in a design file and output a design-specific pin list.  For details, please see IBISWriter documentation:
http://toolbox.xilinx.com/docsan/xilinx4/data/docs/dev/ibis.html

4. All DCI models in "virtex2.ibs" have been generated for specific impedance and PVT conditions.  As variations in PVT change the impedance settings of DCI I/Os, simulation is only valid for the specific conditions outlined in the "dci_pvt_settings.txt" file.  The Vcc supply voltage must be manually set in the IBIS simulator to the specified values to ensure that simulation is accurate.  All SSTL, HSTL, and GTL/P DCI models have been generated for 50 ohms impedance.  DCI LVCMOS models (a.k.a. LVDCI) have been generated for 40 ohms, 50 ohms, 65 ohms, DV2_50 = 25 ohms, and DV2_65 = 32.5 ohms.  Please see the pin list for further details. 


*** Additional Resources

IBIS ANSI/EIA-656-A Home Page:
http://www.eigroup.org/ibis/ibis.htm

'Signal Integrity Central', the Xilinx online resource for SI Engineering: http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?iLanguageID=1&iCountryID=1&title=Signal+Integrity


*** Revision History

rev 3.1 (6/8/04)

Changed C_comp (die capacitance) to 10pF, across all temperatures.  This change is based on physical characterization and examination of the IC layout.

rev 3.0 (4/12/04)

- Integrated non-50 DCI ohm models into virtex2.ibs 
- Added model HSLVDCI_18 (1.8V High-Speed LVDCI).  This is a new IO
  configuration supported in version 6.2is2 of Xilinx implementation 
  software. It consists of an LVDCI driver output, and an HSTL1 input.
- Fixed Vmeas in *40 and *65 LVDCI models

rev 2.9 (1/15/03) - A note about model verification was added.  No model data has been added or changed.

rev 2.8 (5/19/03) - Modified test loads per Xilinx output timing test methodology.  For more information, please see the Virtex-II data sheet, module 3: http://support.xilinx.com/xlnx/xweb/xil_publications_index.jsp
 
rev 2.7 (2/19/03) - Removed the DCILVDS25E model, as it is identical to the DCILVDS25 model.  PLEASE NOTE - This revision was never posted to the web, hence there is no actual "rev 2.7" Virtex-II IBIS file in existence.

rev 2.6 (10/21/02) - Added DCI LVDS input models (DCILVDS25 and DCILVDS25E)

rev 2.5 (9/6/02) - Added 1.8V SSTL models, classes 1 and 2 (DCISSTL18C1_I, DCISSTL18C1_O, DCISSTL18C2_I, DCISSTL18C2_O, SSTL18C1, SSTL18C2)

rev 2.4 (5/2/02) - Following are the changes for this revision:

1. All models account for variation in Vccaux and Vccint:

Min: Vccaux = 3.0V, Vccint = 1.425V
Max: Vccaux = 3.6V, Vccint = 1.575V

2. DCI models were generated for specific PVT conditions.  As fluctuations in voltage and/or temperature change the settings of the DCI output driver (and hence I/V characteristics), simulation is only valid for these specific conditions.  The user must manually set Vcc to the values specified in the [Voltage Range] field to ensure that simulation is accurate.  This is true of all 50 ohm and DV/2 models.  Non-50-ohm models only cover typical PVT conditions.

3. The following DCI models were modified to improve the duty cycle:
-DCIGTL
-DCIGTLP
-DCISSTL2C2
-DCIHSTL1_15
-DCIHSTL2_15
-DCIHSTL3_15
-DCIHSTL4_15
-DCIHSTL1_18
-DCIHSTL2_18
-DCIHSTL3_18
-DCIHSTL4_18

4. Improved the LDT/LVDS models by utilizing voltage-controlled
voltage source to emulate a true differential situation.  The DC values
correlate well with HSPICE simulations.

5. Added [Diff pin] definition for all the differential IO standards.  This includes LVDS, LDT, LVPECL and BUSSLVDS.  This is not a requirement, but is useful for some IBIS simulation tools.

6. Added min and max data to all the differential models.

rev 2.3 (1/08/02) - The following models were modified to improve duty cycle:
-GTL
-GTLP
-SSTL2C2
-HSTL1_15
-HSTL2_15
-HSTL3_15
-HSTL4_15
-HSTL1_18
-HSTL2_18
-HSTL3_18
-HSTL4_18

rev 2.2 (7/31/01) - The models for all I/O standards except LVPECL, 
BUSSLVDS, LVDS25, LVDS25E, LVDS33, LVDS33E, LDT25 have been regenerated 
based on the 1-sigma slow process corner, which is a true representation 
of the slow silicon.  DCI 1.8V HSTL classes 1-4 models have been added.  
The terminated DCI standards have been modified to include the on-chip 
termination. 

rev 2.1 (6/29/01) - The following models have been added:
- HSTL2 1.8V
- HSTL3 1.8V
- HSTL3 1.8V
Regenerated HSTL1 1.8V since the min/typ/max value for Vcco was changed to
1.7/1.8/1.9 from 1.6/1.8/2.0.  Also renamed the 1.5V HSTLs to
- HSTL1_15
- HSTL2_15
- HSTL3_15
- HSTL4_15

rev 2.0 (6/20/01) - The following standards were regenerated: DCI15DV2, 
DCI18DV2, DCI25DV2 and DCI33DV2.  The source termination was corrected 
to 25 ohms (i.e. 50 ohm reference resistors divided by two).

rev 1.9 (6/08/01) - Package parasitics (RLC values) for all packages have been removed as they are not a true representation of the parasitics.  Packaging effects may be modeled using a 65-ohm transmission line with 25-100ps of delay.  This, in conjunction with the R_pkg, L_pkg, and C_pkg values found in the IBIS file (do not change these!), will accurately model BG, FG, FF, and BF packages.  The step is not required for the CS144 pacakge.

rev 1.8 (6/05/01) - DCIHSTL1_O, DCIHSTL2_O, DCIHSTL3_O, and DCIHSTL4_O 
had redundant data in the [pulldown] and [pullup] curves.  This data 
has been removed.

rev 1.7 (5/16/01) - The data in the min (slow-weak) column for all the 
applicable I/O standards has been removed.  The models will be 
regenerated for the min corner once we have more accurate data.

rev 1.6 (5/2/01) - Added package parasitics for BG575 & FF896

rev 1.5 (4/30/01) - Created input and output models for all the DCI 
terminated standards.  Note : The input model has the on-chip termination in the PWR and GND clamp curves.  Version 6.0 of HyperLynx doesn't seem to model on-chip termination correctly.

rev 1.4 (4/18/01) - Added a model for HSTL ClassI 1.8V

rev 1.3 (4/9/01) - IBIS models were regenerated for SSTL2C1, SSTL2C2, SSTL3C1, and SSTL3C2 standards due to incorrect Rfixture values.  The Rfixture had included the series termination for computing the V/T curves which has been omitted.

rev 1.2 (2/7/01) - IBIS models were regenerated for LVPECL and BUSSLVDS due to changes in the bit settings.

2/26/01 - Added the FF896 RLC numbers to the IBIS file.

rev 1.1 (2/1/01) - IBIS models were regenerated for LVCMOS15_16_SLOW, LVCMOS15_16_FAST, LVCMOS18_16_SLOW, LVCMOS18_16_FAST due to changes in the bit settings.

rev 1.0 (12/19/00) - Original IBIS models

